The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to a process for fabricating a P-channel field effect transistor having a metal oxide gate and a gate dielectric with a high dielectric constant while minimizing degradation of the metal oxide gate.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to FIG. 1, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 which is fabricated within a semiconductor substrate 102. The scaled down MOSFET 100 having submicron or nanometer dimensions includes a drain extension junction 104 and a source extension junction 106 formed within an active device area 126 of the semiconductor substrate 102. The drain extension junction 104 and the source extension junction 106 are shallow junctions to minimize short-channel effects in the MOSFET 100 having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET 100 further includes a drain contact junction 108 with a drain silicide 110 for providing contact to the drain of the MOSFET 100 and includes a source contact junction 112 with a source silicide 114 for providing contact to the source of the MOSFET 100. The drain contact junction 108 and the source contact junction 112 are fabricated as deeper junctions such that a relatively large size of the drain silicide 110 and the source silicide 114 respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET 100. The drain and source extension junctions 104 and 106 and the drain and source contact junctions 108 and 112 are doped with an N-type dopant for an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor) and with a P-type dopant for a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor).
The MOSFET 100 further includes a gate dielectric 116 and a gate electrode 118 which may be comprised of polysilicon. A gate silicide 120 is formed on the polysilicon gate electrode 118 for providing contact to the gate of the MOSFET 100. The MOSFET 100 is electrically isolated from other integrated circuit devices within the semiconductor substrate 102 by shallow trench isolation structures 121. The shallow trench isolation structures 121 define the active device area 126, within the semiconductor substrate 102, where the MOSFET 100 is fabricated therein.
The MOSFET 100 also includes a spacer 122 disposed on the sidewalls of the gate electrode 118 and the gate dielectric 116. When the spacer 122 is comprised of silicon nitride (Si3N4), then a spacer liner oxide 124 is deposited as a buffer layer between the spacer 122 and the sidewalls of the gate electrode 118 and the gate dielectric 116.
As the dimensions of the MOSFET 100 are scaled down to tens of nanometers, short-channel effects degrade the performance of the MOSFET 100. Short-channel effects that result due to the short length of the channel between the drain extension junction 104 and the source extension junction 106 of the MOSFET 100 are known to one of ordinary skill in the art of integrated circuit fabrication. The electrical characteristics of the MOSFET 100 become difficult to control with bias on the gate electrode 118 with short-channel effects which may severely degrade the performance of the MOSFET.
Conventionally, the gate dielectric 116 for the MOSFET 100 is typically comprised of silicon dioxide (SiO2), and the gate electrode 118 is typically comprised of polysilicon. As the channel length and width dimensions of the MOSFET 100 are scaled down for enhanced speed performance, the thicknesses of the gate dielectric 116 and the gate electrode 118 are also correspondingly scaled down, as known to one of ordinary skill in the art of integrated circuit fabrication. However, as the channel length and width dimensions of the MOSFET 100 are scaled down to tens of nanometers, the thickness of the gate dielectric 116 is also scaled down to tens of angstroms when the gate dielectric 116 is comprised of silicon dioxide (SiO2). With such a thin gate dielectric 116, charge carriers easily tunnel through the gate dielectric 116, as known to one of ordinary skill in the art of integrated circuit fabrication.
When charge carriers tunnel through the gate dielectric 116, gate leakage current undesirably increases resulting in increased static power dissipation and even circuit malfunction. In addition, with charge carriers tunneling through the gate dielectric 116, decreased charge carrier accumulation in the channel of the MOSFET may result in undesirable increase in resistance through the channel of the MOSFET. Furthermore, with the thin gate dielectric 116, charge accumulation at the gate electrode 118 causes an undesirable increase in charge carrier scattering at the surface of the channel of the MOSFET 100. Such increase in charge carrier scattering in turn results in higher resistance through the channel of the MOSFET.
In light of these disadvantages of the thin gate dielectric 116 when the gate dielectric 116 is comprised of silicon dioxide (SiO2), referring to FIG. 2, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 150 has a gate dielectric 152 comprised of a dielectric material having a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO2) (i.e., a high dielectric constant material) when the MOSFET 150 has scaled down dimensions of tens of nanometers. Device structures having the same reference number in FIGS. 1 and 2 refer to elements having similar structure and function. A dielectric material having a higher dielectric constant has higher thickness for achieving the same capacitance. Thus, when the gate dielectric 152 is comprised of a high dielectric constant material, the gate dielectric 152 has a higher thickness (hundreds of angstroms) than when the gate dielectric is comprised of silicon dioxide (SiO2) (tens of angstroms), for field effect transistors having scaled down dimensions of tens of nanometers.
The gate dielectric 152 with high dielectric constant has higher thickness to minimize charge carrier tunneling through the gate dielectric 152 for field effect transistors having scaled down dimensions of tens of nanometers. Charge carrier tunneling through the gate dielectric 152 is minimized exponentially by the thickness of the gate dielectric. Dielectric materials having a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO2) are known to one of ordinary skill in the art of integrated circuit fabrication.
However, typical dielectric materials having a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO2) react with the polysilicon gate at temperatures above about 800xc2x0 Celsius. Thus, referring to FIG. 2, a metal gate electrode 154 is formed instead of a polysilicon gate electrode for an NMOSFET. A metal gate electrode 154 comprised of one of aluminum, molybdenum, platinum, or tantalum is advantageous for an NMOSFET. When such a metal is used for the gate electrode of an NMOSFET, the gate electrode of a PMOSFET is advantageously comprised of a metal oxide including one of ruthenium oxide (RuO2) or iridium oxide (IrO2) for proper work function relations between the NMOSFET and the PMOSFET. The gate dielectric 152 comprised of a dielectric material having a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO2) is less likely to react with the metal gate electrode 154 of the NMOSFET.
Nevertheless, the gate electrode comprised of metal oxide for the PMOSFET may still react with the high dielectric constant material of the gate dielectric at temperatures above about 800xc2x0 Celsius. A thermal anneal process for activating dopant within the drain and source junctions of the field effect transistor and a silicidation process for forming drain and source silicides uses temperatures above about 1000xc2x0 Celsius. In addition, a thermal anneal with hydrogen gas (H2) is performed toward the end of the process for fabricating integrated circuits to strengthen the reliability of dielectric materials of the integrated circuit, as known to one of ordinary skill in the art of integrated circuit fabrication. When the gate electrode is comprised of a metal oxide for the PMOSFET, the hydrogen may react with the metal oxide of the gate electrode for the PMOSFET to degrade the gate electrode.
Thus, a mechanism is desired for forming a gate electrode comprised of metal oxide for the PMOSFET and a gate electrode comprised of metal for the NMOSFET with minimized degradation of the gate electrode comprised of metal oxide for the PMOSFET.
Accordingly, in a general aspect of the present invention, the gate electrode comprised of metal oxide for the PMOSFET is formed after the thermal anneal process for activating dopant within the drain and source junctions of the field effect transistor and after the silicidation process for forming drain and source silicides. In addition, an insulating material is deposited to encapsulate the gate electrode comprised of metal oxide for the PMOSFET before the thermal anneal using hydrogen gas (H2) to prevent contact of the hydrogen gas with the gate electrode comprised of metal oxide for the PMOSFET.
In one embodiment of the present invention, for fabricating a PMOS (P-channel Metal Oxide Semiconductor) field effect transistor on a semiconductor substrate, a layer of gate dielectric material is deposited on the semiconductor substrate, and a layer of dummy gate electrode material is deposited on the layer of gate dielectric material. The layer of gate dielectric material and the layer of dummy gate electrode material are patterned over a first active device area of the semiconductor substrate to form a PMOS (P-channel Metal Oxide Semiconductor) gate dielectric from the gate dielectric material and to form a PMOS (P-channel Metal Oxide Semiconductor) dummy gate electrode from the dummy gate electrode material. A drain and source P-type dopant is implanted into exposed regions of the first active device area of the semiconductor substrate to form a PMOS (P-channel Metal Oxide Semiconductor) drain junction and a PMOS (P-channel Metal Oxide Semiconductor) source junction. A thermal anneal is performed to activate the drain and source P-type dopant within the PMOS drain and source junctions. A PMOS (P-channel Metal Oxide Semiconductor) drain silicide is formed with the PMOS drain junction, and a PMOS (P-channel Metal Oxide Semiconductor) source silicide is formed with the PMOS source junction, in a silicidation process.
In addition, an insulating material is deposited to surround the PMOS dummy gate electrode and the PMOS gate dielectric. The PMOS dummy gate electrode is etched away to form a PMOS (P-channel Metal Oxide Semiconductor) gate electrode opening surrounded by the insulating material. The PMOS gate electrode opening is filled with a metal oxide material to form a PMOS metal oxide gate electrode after the thermal anneal process for activating the drain and source P-type dopant within the PMOS drain and source junctions and after the silicidation process for forming the drain and source silicides. The thermal anneal process for activating the drain and source P-type dopant within the PMOS drain and source junctions and the silicidation process for forming the drain and source silicides may use temperatures above about 1000xc2x0 Celsius. Such high temperature processes are performed with the dummy gate electrode, and the PMOS metal oxide gate electrode is formed after such high temperature processes. In this manner, the PMOS metal oxide gate electrode is not heated up to such high temperatures to minimize degradation of the PMOS metal oxide gate electrode.
In another aspect of the present invention, an insulating material is deposited on top of the PMOS metal oxide gate electrode to encapsulate the PMOS metal oxide gate electrode before performing a thermal anneal with hydrogen gas. Thus, the PMOS metal oxide gate electrode is encapsulated to prevent exposure of the PMOS metal oxide gate electrode to the hydrogen gas to minimize degradation of the PMOS metal oxide gate electrode.
In a further aspect of the present invention, an NMOS (N-channel Metal Oxide Semiconductor) field effect transistor is also fabricated by patterning the layer of gate dielectric material and the layer of dummy gate electrode material over a second active device area of the semiconductor substrate to form an NMOS (N-channel Metal Oxide Semiconductor) gate dielectric from the gate dielectric material and to form an NMOS (N-channel Metal Oxide Semiconductor) dummy gate electrode from the dummy gate electrode material. A drain and source N-type dopant is implanted into exposed regions of the second active device area of the semiconductor substrate to form an NMOS (N-channel Metal Oxide Semiconductor) drain junction and an NMOS (N-channel Metal Oxide Semiconductor) source junction.
A thermal anneal process is performed to activate the drain and source N-type dopant within the NMOS drain and source junctions. An NMOS (N-channel Metal Oxide Semiconductor) drain silicide is formed with the NMOS drain junction, and an NMOS (N-channel Metal Oxide Semiconductor) source silicide is formed with the NMOS source junction, in a silicidation process. The thermal anneal process for activating the drain and source N-type dopant within the NMOS drain and source junctions and the silicidation process for forming silicides of the NMOSFET are performed before the PMOS metal oxide gate electrode is formed to minimize degradation of the PMOS metal oxide gate electrode.
An insulating material is deposited to surround the NMOS dummy gate electrode and the NMOS gate dielectric. The NMOS dummy gate electrode is etched away to form an NMOS (N-channel Metal Oxide Semiconductor) gate electrode opening surrounded by the insulating material. The NMOS gate electrode opening is filled with a metal material to form an NMOS metal gate electrode.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.